1. Field of the Invention
The present invention relates to a complementary metal-oxide semiconductor integrated circuit device and more particularly, relates to an improvement of an arrangement of a unit cell and a manner of isolation between functional devices in a complementary metal-oxide semiconductor integrated circuit device in which a plurality of unit cells, such as a transistor array and a gate array are juxtaposed.
2. Description of the Prior Art
FIG. 1 shows an arrangement of a gate array in a conceptual manner. The gate array comprises an input-output circuit portion 1, an internal wiring portion 2 and an internal gate circuit portion 3. The internal gate circuit portion 3 is adapted such that a plurality of unit cells are juxtaposed. Generally, the internal gate circuit portion 3 may include a single type of unit cell or may include a plurality of types of unit cells. A functional device having a logic function is structured by a single unit or cell by a plurality of unit cells, or a plurality of functional devices are formed within a unit cell. A plurality of functional devices thus structured are interconnected by an internal wiring provided in the internal wiring portion 2 and, in addition, are connected to an input-output circuit existing in the input-output circuit portion 1, so that a logic circuit is structured.
FIG. 2 shows an example of a conventional arrangement of unit cells. A unit cell 30 encircled by a dotted line is structured to include gate regions 31a and 31b, regions 32a and 32b to become a source or a drain, to constitute a metal-oxide semiconductor transistor, and isolation regions 33 for electrically isolating the unit cell 30 from another unit cell adjacent thereto. A portion 34 encircled by a dotted chain line has a conductivity type opposite to that in a semiconductor substrate other than this portion 34, which is generally called a well. Usually, an N-type semiconductor substrate is used and thus P-type impurities are introduced into the portion 34. As a result, an N-channel metal-oxide semiconductor transistor is formed in the portion 34 encircled in a dotted chain line and a P-channel metal-oxide semiconductor transistor is formed on the semiconductor substrate side outside the portion 34. In the FIG. 2 example, three pairs of gate regions 31a and 31b are disposed in the unit cell 30, and thus a functional gate having a maximum of three inputs can be structured. However, in the FIG. 2 example, if a functional gate, a flip-flop and the like having four or more inputs are desired, a plurality of unit cells 30 must be used.
FIG. 3A shows a schematic diagram of a NOR gate having four inputs, which is structured by the above described FIG. 2 example, and FIG. 3B shows an equivalent circuit of the NOR gate having four inputs in FIG. 3A. As seen from FIGS. 3A and 3B, interconnections between metal-oxide semiconductor transistors as included in the NOR gate having four inputs are provide by a first layer of aluminum wiring including a wiring pattern having elements 41a, 41b and 411, together with another aluminum wiring pattern 42 of a second layer for providing four inputs and one output. More particularly, four N-channel metal-oxide semiconductor transistors .theta.1a, .theta.2a, .theta.3a and .theta.4a are connected in series, wherein the ground potential GND is applied to the source region of the transistor .theta.4a through the first layer aluminum wiring 41a. On the other hand, four P-channel metal-oxide semiconductor transistors .theta.1b, .theta.2b, .theta.3b and .theta.4b are connected in parallel, to which the V.sub.DD potential is applied through the first layer aluminum wiring 41b. The gate regions of the P- and N-channel transistors in each pair are connected in common by the second layer aluminum wiring 42. Referring to FIG. 3A, four inputs IN1 to IN4 are applied to the gate electrodes 31a, 31b, 31c and 31d in the N-channel and P-channel metal-oxide semiconductor transistors through the second layer aluminum wiring 42 from the internal wiring portion 2 as shown in FIG. 1, and the output OUT is sent out to the internal wiring portion 2 through the second layer aluminum wiring 42. In the first layer aluminum wiring regions 41a and 41b are connected to the N-type or P-type source or drain regions 32a, 32c, and 32b, 32d, formed in the surface of the semiconductor substrate, by contact holes 51. The connection of the second layer aluminum wiring 42 and the gate regions 31a, 31b, 31c and 31d are made at the connecting points 52.
With such a conventional structure, there must be provided an isolation region 33 for electrically isolating a unit cell 30 from another unit cell adjacent thereto. Therefore, for example, if and when the NOR gate having four inputs is structured, three pairs of gate regions 31a and 31b and a pair of gate regions 31c and 31d are needed, which means that it is necessary to combine two unit cells 30. More particularly, two wirings 411 are needed for the purpose of making electrically equal the potential at the source or drain regions 32a and 32c in the N-channel metal-oxide semiconductor transistors and the source or drain regions 32b and 32d in the P-channel metal-oxide semiconductor transistors included in both unit cells 30. In addition, the source or drain regions in the portions to be connected by the wirings 411 become larger in area than the source or the drain regions in the remaining portions and thus stray capacitance between a semiconductor substrate or the above described well and such regions is increased, whereby signals are delayed and the operating speed of a functional gate decreases.